FIG. 3 is a circuit diagram showing the configuration of an overcurrent protection apparatus of a related art. The overcurrent protection apparatus shown in the figure is provided in a load circuit which includes a power supply VB, a load RL and a semiconductor switch T11 formed by an FET. The overcurrent protection apparatus interrupts the semiconductor switch T11 to protect the load circuit when an overcurrent flows into the load circuit. This operation will be explained concretely.
The overcurrent protection apparatus includes a MOSFET (T12) constituting a multi-source FET with respect to the semiconductor switch T11. The drain of the MOSFET (T12) is connected to the power supply VB, and a connecting point Y1 of the MOSFET (T12) and the power supply VB is connected to the drain of the semiconductor switch T11. The source of the MOSFET (T12) is grounded via a resistor Rr. The gate of the MOSFET (T12) is connected to the gate of the semiconductor switch T11 at a connecting point Y2. The connecting point Y2 is connected to the output terminal of a driver 112 via a resistor R1.
A latch DF1 formed by an AND circuit AND1, a switch SW1, a resistor R2 and a D flip-flop is provided on the input side of the driver 112. The switch SW1 and the resistor R2 are coupled in series, and the serially coupled circuit is provided between the power supply VB and the ground. The connecting point of the switch SW1 and the resistor R2 is connected to one of the input terminals of the AND circuit AND1. The one of the input terminals of the AND circuit AND1 is also connected to the reset terminal of the latch DF1. Further, the other of the input terminals of the AND circuit AND1 is connected to the output terminal (Q_bar) of the latch DF1.
The source of the semiconductor switch T11 is connected to the negative side input terminal of a comparator CMP1, the positive side input terminal of the comparator CMP1 is connected to the source of the MOSFET (T12), and the output terminal of the comparator CMP1 is connected to the input terminal of the latch DF1.
Hereinafter, the operation of the load circuit including the overcurrent protection apparatus shown in FIG. 3 will be explained. When the switch SW1 is turned on, since the output of the latch DF1 is at a high (H) level at this time, the output of the AND circuit AND1 becomes an H level, whereby the driver 112 supplies a charge pump voltage to the gate of the multi-source FET (common gate of T11 and T12).
Thus, the semiconductor switch T11 is turned on and so a load current ID flows therethrough. Further, since the MOSFET (T12) is also turned on, a reference signal Iref flows through the MOSFET (T12). The MOSFET (T12) constituting the multi-source FET has the same characteristics as the semiconductor switch T11 and the channel width thereof is normally set in a range between ( 1/2000) and ( 1/1000) of the channel width of T11. Supposing that (channel width of T11)/(channel width of T12) is n, n is in a range between 1,000 and 2,000.
Supposing that the source voltages of the semiconductor switch T11 and the MOSFET (T12) are VSA and VSB respectively, ID becomes n*Iref when VSA is equal to VSB. The value of the voltage VSA depends on the resistance value of the load RL, and the value of the voltage VSB depends on the value of the resistor Rr. The value of the resistor Rr is set in a manner that the voltage VSA is larger than the voltage VSB in the normal state of the load RL and the wiring of the load circuit. Thus, in the normal state, since the voltage supplied to the negative side input terminal of the comparator CMP1 is larger than the voltage supplied to the positive side input terminal thereof, the output of the comparator CMP1 is held at a low (L) level.
When a wiring between the semiconductor switch T11 and the load RL is short-circuited to the ground in a state where the load current ID flows, the load current ID is increased and the voltage VSA becomes smaller than the voltage VSB, whereby the output of the comparator CMP1 changes into the H level and so the output of the latch DF1 becomes the L level. Thus, since the output of the AND circuit AND1 becomes the L level, the output terminal of the driver 112 is grounded, so that the gate of the multi-source FET (common gate of T11 and T12) is grounded through the resistor R1 and hence each of the semiconductor switch T11 and the MOSFET (T12) is turned off. As a result, since a short-circuit current is interrupted, the wiring and the semiconductor switch T11 can be protected from the overcurrent.
In the case where multi-source FET (T11, T12) is normal, the wiring of the load circuit and the semiconductor switch T11 can be protected by the overcurrent detection function. However, when the on-resistance value of the semiconductor switch T11 increases abnormally, the wiring and the semiconductor switch T11 can not be protected by the overcurrent detection function as to such the abnormality
The following case is supposed as a cause of abnormally increasing of the on-resistance value. That is, each of the semiconductor switch T11 and the MOSFET (T12) is configured by many small FETs (hereinafter called element FETs) coupled in parallel. When the insulation film of the gate of a part of the element FETs is broken and the connection between the gate and the body thereof is short-circuited, a small leak current flows between the gate and the body, that is, between the gate and the source. The leak current flows through the resistor R1 coupled in series with the gate to thereby cause a voltage drop across the resistor R1. When the breakage of the element FET advances and the leak current increases, the voltage drop across the resistor R1 increases to thereby reduce the voltage between the gate and the source of each of the semiconductor switch T11 and the MOSFET (T12). Since the gate of the semiconductor switch T11 and the gate of the MOSFET (T12) are connected to each other, each of the on-resistance values of the semiconductor switch T11 and the MOSFET (T12) increases in the similar manner and a shunt-current ratio therebetween does not change.
Supposing that the resistance value of the load RL is 20, when the output voltage of the power supply VB is 12 volt, the load current ID becomes 6 ampere, and the on-resistance value of the FET usually used with respect to the load RL is about 10 mΩ. If the on-resistance value increases to 100 mΩ from 10 mΩ due to the leak current between the gate and the body, the load current ID becomes 12 V/(2Ω+0.1Ω)=5.71 ampere. Since the load current ID is 12 V/(2Ω+0.01Ω)=5.97 ampere in the normal state, the load current ID reduces by 0.26 ampere.
The comparator CMP1 detects the increase of the current but can not detect the reduction of the current. Even if a comparing unit (comparator) is added in order to detect the reduction of the current, since the voltage change between the source voltages VSA and VSB due to the reduction of 0.26 ampere is a small value of about 26 mV, it is difficult to accurately detect the current reduction to turn off the FET while avoiding the erroneous determination. On the other hand, since an amount of heat generated from each of the semiconductor switch T11 and the MOSFET (T12) becomes about ten times as large as that in the normal state, each of the semiconductor switch T11 and the MOSFET (T12) is broken when such the state is left as it is for a long time. An overheat interrupting function is incorporated into the semiconductor switch T11 in order to prevent such the breakage. That is, the overheat interrupting function is an indispensable constituent element in a current sensor using the multi-source FET.
Summarizing the aforesaid contents, when the semiconductor switch is disposed on the high-side of the load, that is, between the power supply and the load, the following methods have been employed as methods of protecting the semiconductor switch and the connecting wiring between the semiconductor switch and the load.
(1) The detecting unit for detecting the current flowing through the semiconductor switch is provided to turn off the element when the overcurrent exceeding the normal current range flows. As the method of detecting the overcurrent, there are the method of adding the shunt resistor in series with the element to directly detect the current flowing through the element and the method of determining the overcurrent by using the current which is obtained by dividing the current flowing through the element at the constant shunt-current ratio. The latter method is realized by using the multi-source FET etc.
(2) In the case where a large overcurrent flows due to the dead short-circuit etc., the element may be broken by the heat loss before the overcurrent is detected and the element is turned off. Further, when the on-resistance value of the element increases by any reason, the temperature of the element may exceed the allowable temperature (absolute rated value) due to self-heating even by a current lower than the overcurrent determination value. As a countermeasure against these problems, there is provided with the overcurrent interrupting function for interrupting the current flowing through the element when the temperature of the element exceeds the predetermined temperatures.
The semiconductor switch is advantageous in the miniaturization and the small amount of heat generation due to no-utilization of a fuse. However, in the conventional technique, as described above, the semiconductor switch requires the two kinds of detecting processes for detecting the current and the temperature in the overcurrent protection, which causes the increase of the cost of the semiconductor switching element. Thus, since the cost of the semiconductor switching element is higher to a large extent as compared with the cost of the simple configuration of the fuse and the relay, the spread of the semiconductor switching element is impeded.
JP-A-2004-48498 (patent literature 1) discloses the technique relating to the aforesaid overcurrent protection apparatus. The patent document 1 discloses a technique in which a critical voltage is obtained from a product of the on-resistance value of a semiconductor switch and the minimum current value when the channel temperature of the semiconductor switch reaches the upper limit of a permissible temperature, and the semiconductor switch is turned off at a time point before the voltage reaches the critical voltage to thereby protect the semiconductor switch.    Patent Literature 1: JP-A-2004-48498